1. Field of the Invention
The present invention relates to semiconductor memory devices, and more specifically to a non-volatile semiconductor memory device having memory cells that each include a floating gate transistor serially connected to a selection transistor and a process for manufacturing the same.
2. Description of Related Art
The memory cells of a conventional non-volatile semiconductor memory device each include a floating gate transistor having an active area, source/drain regions, and a control gate coupled to a floating gate. The floating gate transistor is serially connected to a selection transistor. Double-poly technology is widely used in the manufacturing of such non-volatile memory devices (e.g., EPROMs, EEPROMs, or Flash-EEPROMs) to realize the floating gate transistors.
Conventionally, in order to realize a memory device including non-volatile memory cells in a double-poly technology, it is necessary to use a set of standard CMOS process masks that include at least the following masks: POLY1 mask for defining the floating gates, MATRIX (or interpoly dielectric) mask to remove the interpoly dielectric protection of the memory array, and POLY2 (or control gates) mask for defining the poly lines that form the control gates of the memory cells. Other masks are usually also necessary for manufacturing a specific kind of non-volatile memory cell. For example, a specific mask for N+ implant is required for EEPROMs, implant masks are required for source and/or drain junction engineering in Flash-EFPROMs, and a Self-Aligned-Source mask is used to obtain a source diffusion aligned to the polysilicon lines.
Because the mask count is a cost issue for economic production, and also because the increasing number of metallization levels required for interconnections is impacting the cycle-time in the production line, it is desirable to reduce the number of masks required to realize a non-volatile memory cell, while at the same time maintaining the same cell features. However, a problem specifically related to the manufacturing of non-volatile memory cells with a compact layout concerns the POLY1 mask. With reference to FIGS. 1A through 1D, the POLY1 mask is used to cross the active area on the diffusion region used as a source line for the memory array.
The floating gates must be defined in a direction that is parallel to the word lines, and this is obtained by etching the poly1 layer with a sufficient extension beyond the future control gate line. In this manner, assuming a "self-aligned" process, any short between floating gates of adjacent cells is avoided when the floating gate is defined in the other direction by the poly2/interpoly/poly1 stack etching. Therefore, in the regions in which POLY1 crosses the active areas, no poly1 layer is left on the active area and during the stack etching a consistent substrate etching is provided by the trench 20, as shown in FIG. 1B. This substrate etching is unavoidable because poly2 etching can be stopped on interpoly dielectric, while the interpoly dielectric etch is stopped on poly1, but in the overlapping regions poly1 is not present and the etching is stopped only on the active area.
As a result, the interpoly dielectric etching is stopped on the silicon substrate, but during the poly1 etching the substrate is also etched. For this reason, the source line will not be flat and, even if this is not a severe problem because an N+ implant for source and drain can guarantee the electrical continuity of the source line, there is a serious drawback in that the source resistance is increased as compared to a typical N+ diffusion of a flat cross section. Moreover, if the manufacturing process includes a phase of active area salicidation (as in most advanced technologies now used), the source line irregularity can cause further problems due to reaction of the metal (i.e., Ti) with silicon. More particularly, the metal reaction involves regions with a low doping concentration (e.g., the bottom comer of the etched source line portion), so a short between the N+ diffused substrate region can occur.
The problem of silicon etching in the source line and the corresponding increase in the source resistance is particularly severe in the case of EEPROM memory devices for which the bits of the same byte must be adjacent for construction. Moreover, the control gates are separated at byte level in order to allow byte granularity both in write and erase phases. The inability to divide the bits leads to an enhanced series resistance effect during the reading phase, because all the bits of the same byte can drain current and a correspondingly increased voltage drop on the source line occurs. The only possible solution that has been proposed is to introduce more frequent source contacts. However, this causes a corresponding overall circuit area increase of the memory device.